High Speed Scaleable Multiplier to Reduce Power Consumption

Description

Multipliers, being the fundamental building blocks in digital signal processing, can be useful for trading off power dissipation against speed and functional operation of the system, so the system can continue to be used in a gracefully degraded fashion, even when the battery charge is low. The algorithm in this high speed multiplier (HSM) uses a folding technique, which gives the unique ability for this tradeoff.

Advantages

• Ability to tradeoff area, power dissipation, and speed against each other
• Allows portable electronic systems to be used longer and more efficiently in a degraded yet operational fashion, and at a smaller size
• Folding technique reduces the range over which squaring is done
• HSM16-bit and HSM 32-bit have significantly lower power dissipation and comparable speed, relative to the Wallace Multiplier and Array Multiplier implementations

Potential Applications

• Power management in mobile embedded systems, such as cell phones, PDAs, and other wireless/portable systems, is considered to be one of the 5 major design challenges by the semiconductor industry forum. This power-aware multiplier provides a solution to some of the power system problems, and therefore can be applied to mobile electronic devices

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Inventor
Dr. Ravi Shankar
Computer Science & Engineering

IP Status
U.S. Patent 7,080,114 Issued7/18/2006

U.S. Patent Application
Filed 12/04/2001

Kurt R. Moore
Assistant V.P. & Director
Ph: 561-297-1165
Fax: 561-297-2141
kmoore34@fau.edu

Michelle Webb
Assistant Director
Ph: 561-297-0673
Fax: 561-297-2141
mwebb18@fau.edu

Case Number
2003-17, 1999-18